This application claims the priority benefit of Taiwan application serial no. 87119250, filed Nov. 20, 1998, the full disclosure of which is incorporated herein by reference.
1. Field of Invention
The present invention generally relates to a placement method for an arrayed-element device, and more particularly to an automatic placement of standard cells for an arrayed-element device, which can generate a schematic script based on a circuit topology of the arrayed-element device.
2. Description of Related Art
Thanks to the advancements from semiconductor technologies, complicated circuits with significantly improved operating speed can now be built into a single integrated circuit (IC) package.
As circuit complexities of the ICs increase, it becomes unrealistic to use a real wiring as usually adopted in the past to verify the feasibility of the designed circuitry. Nowadays, computer-aided tools are widely used to facilitate circuit designs. For example, circuits are designed based on required specifications with the help of circuit design programs. A circuit simulation program is then used to verify the logical functions of the circuits designed. When the logical functions of the designed circuit are verified as correct, a place and route (PandR) program is used to perform routings for the circuitry, so that the designed circuit can be fabricated into an IC.
Because the transmission time delay of signals between components within a circuit needs to be considered in a practical circuit, resistor and capacitor (RC) values of components in the circuit need to be extracted to perform a sdf backannotation simulation. This process is to make sure that the routing for the circuit meets the time delay requirements.
Although PandR tools and software available are powerful, there exist, however, some deficiencies in the handling of some particular circuits, for example, an arrayed-element device which has a symmetrical structure. There are many kinds of arrayed-element devices, among which is a First-In-First-Out (FIFO) memory. The FIFO memory is generally used as a data or program queue. Data or program are fed into the input ports and read from the output ports of the FIFO memory in a first-in, first-out order. To allow a correct data flow between stages in the FIFO memory, a timing sequence needs to be kept correct at all times.
FIG. 1 shows the structure of a conventional First-In-First-Out (FIFO) memory 100, which comprises an n-bits data width B0xcx9cBnxe2x88x921 and an m-stages depth. There is a plurality of data units 110 in the FIFO memory 100, each storing one-bit data. A column of data units 110 constitutes a one-stage memory, which stores n-bits of data. The data units 110 in every stage of the FIFO memory 100 are controlled by a control unit 120. To minimize the signal transmission delay, the control unit 120 is positioned in the middle each stage. Data B0xcx9cBnxe2x88x921 are propagated sequentially from the first stage through the mth stage, from which an output is obtained.
FIG. 2 shows a block diagram of a data unit 110 in the FIFO memory 100 in FIG. 1. As shown in FIG. 2, the data unit 110 comprises a buffer 112 and a latch 114. The data unit 110 receives data from an input port I into the buffer 112. The latch 114, which is controlled by a control signal E, latches the data from the buffer 112 so that data can be obtained from an output port O of the latch 114.
For an arrayed-element device like the above-mentioned FIFO memory 100 in FIG. 1, which has a data width of 64 bits and a depth of 32 stages, there are 64xc3x9732 data units 110 arranged in an orderly manner. The data unit 110 latches data received from its previous stage through the control signal E. Therefore, placement of data units is essential for data to be correctly transmitted through stages in the memory. Fail to obtain a regular placement for the data units will result in an adverse effect on the smooth operation of the FIFO memory 100.
Unfortunately, automatic PandR programs generally do not take into account the above-mentioned characteristics of the arrayed-element device during the placement and routing processes. As a result, a manual, instead of automatic, placement and routing for the arrayed-element device is used in order to obtain a better performance.
Because the automatic PandR program, for example, the XO PandR tool, is not suitable for manual placement and routing, therefore other software tools, for example, the tool OPUS, are used to perform the manual placement and routing for the arrayed-element device. The arrayed-element device after placement and routing is fed into the automatic PandR tool as a hard macro, and can only be treated as a black box. The automatic PandR tool subsequently completes all the remaining placement and routing tasks for the whole IC.
Since the arrayed-element device is regarded as a black box, the RC extraction can not be directly performed. Instead, a GDS file as an interchange format needs to be created before the RC extraction can be performed to generate a standard delay format (SDF) for circuit simulation of the arrayed-element device. However, these tasks are time consuming. The manual PandR process requires a time frame of about a week per FIFO, and the conversion to a GDS file requires another 2 to 3 days for a whole chip. For an extremely tight design schedule of ICs, the time frame required for these extra tasks seriously affects the developing schedule.
As a summary, the conventional method of manual PandR for the arrayed-element device has the following disadvantages:
1. Because of the characteristics of the arrayed-element device, manual placement and routing are inevitable. Therefore, extra time frame is required, which consequently lengthens the developing schedule.
2. The arrayed-element device after manual placement and routing is regarded as a black box to be fed into the automatic PandR tool. A GDS file as an interchange format needs to be generated for a RC extraction. The conversion to the GDS file takes extra time, which delays the developing schedule of the product.
It is therefore an objective of the present invention to provide a method of automatic placement for an arrayed-element device, which automatically generates a schematic script based on topological specifications of the arrayed-element device. The schematic script can be loaded into an automatic PandR tool to perform an automatic routing so as to reduce the time required by manual PandR and file format conversion.
In accordance with the foregoing and other objectives of the present invention, a method of automatic placement for an arrayed-element device, in which standard cells are placed into rows in a circuit layout, is provided. The method comprises the steps of: loading parameters of the arrayed-element device, determining if submodules can be placed in a row for the arrayed-element device, and generating a schematic script. The schematic script can be loaded into an automatic PandR tool, which subsequently completes PandR for the whole IC.
According to a preferred embodiment of the present invention, the step of loading parameters of the arrayed-element device comprises reading in width information of standard cells, reading in topological specifications of the arrayed-element device, reading in a netlist which comprises information of a plurality of modules, and locating a top module from the netlist. When topological specifications are read in, an origin coordinate, height and width information of the standard cells, and topological information of the arrayed-element device is recorded accordingly.
When the netlist is read in, connecting ports of every module, instances within a module, space required for every module, and connecting relationship between instances are recorded accordingly.
According to a preferred embodiment of the present invention, the step of determining if submodules can be placed in a row for the arrayed-element device comprises: locating a submodule with the largest dimensions within the module, deciding whether other submodules exist, deciding if the submodule occupies only one row if there is a submodule, returning to the step of deciding whether other submodules exist if the submodule occupies more than one row, and storing all instances of the submodule into a data table if the submodule occupies only one row and then returning to the step of deciding whether other submodules exist.
Furthermore, the step of generating a schematic script comprises the steps of:
initializing a coordinate;
initializing a topological row variable;
deciding whether the topological row variable is larger than the total topological rows required for placement;
exiting if the row variable is larger than the total rows;
performing the following steps if the topological row variable is smaller than or equal to the total rows:
locating a first instance of the row that the row variable refers to; determining row of layout and placement method for the instance;
generating the schematic script of all standard cells for the instance;
deciding whether there exist any other instances in the row referred to by the row variable;
increasing the topological row variable by one and returning to the step of deciding whether the row variable is larger than the total rows if there exists no other instances in the row referred to by the row variable; and
locating a next instance and examining connection relationship of the next instance if there is an instance in the row referred to by the row variable, and then returning to the step of determining what number of rows is required and a placement method for the instance.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.